(Hong Kong)
Product Summary
The 74HC11 is a triple 3-input AND gate. The 74HC11D is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC11D is specified in compliance with JEDEC standard no. 7A. The 74HC11D provides the 3-input AND function.
Parametrics
74HC11 absolute maximum ratings: (1)VCC supply voltage -0.5 to +7V; (2)IIK input clamping current VI＜-0.5V or VI＞VCC + 0.5V[1]: ±20mA; (3)IOK output clamping current VO＜-0.5V or VO＞VCC + 0.5V[1]: ±20mA; (4)IO output current -0.5 V＜VO＜VCC + 0.5V: ±25mA; (5)ICC supply current: - 50mA; (6)IGND ground current: -50mA; (7)Tstg storage temperature: -65 to +150℃; (8)Ptot total power dissipation [2] DIP14 package: 750mW; (9)SO14 and (T)SSOP14 packages: 500mW.
Features
74HC11 features: (1)Input levels: For 74HC11: CMOS level; (2)For 74HCT11: TTL level; (3)ESD protection: HBM JESD22-A114F exceeds 2000V; (4)MM JESD22-A115-A exceeds 200V; (5)Multiple package options; (6)Specified from -40℃ to +85℃ and from -40℃ to +125℃.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||||||||
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 74HC112D |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
Negotiable |
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74HC112D,652 |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
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74HC112D,653 |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
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74HC112DB |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
Negotiable |
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74HC112DB,112 |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
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74HC112DB,118 |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
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74HC112DB-T |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
Negotiable |
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74HC112D-T |
NXP Semiconductors |
Flip Flops DUAL J-K NEG EDGE |
Data Sheet |
Negotiable |
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