AD9233BCPZ-125

Product Summary

The AD9233BCPZ-125 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The AD9233BCPZ-125 uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range. The applications of the AD9233BCPZ-125 include Ultrasound equipment, IF sampling in communications receivers IS-95, CDMA-One, IMT-2000, Battery-powered instruments, Hand-held scope-meters, Low cost digital oscilloscopes.

Parametrics

AD9233BCPZ-125 absolute maximum ratings: (1)AVDD to AGND: -0.3 V to +2.0 V; (2)DRVDD to DRGND: -0.3 V to +3.9 V; (3)AGND to DRGND: -0.3 V to +0.3 V; (4)AVDD to DRVDD: -3.9 V to +2.0 V; (5)D0 through D11 to DRGND: -0.3 V to DRVDD + 0.3 V; (6)DCO to DRGND: -0.3 V to DRVDD + 0.3 V; (7)OR to DRGND: -0.3 V to DRVDD + 0.3 V; (8)CLK+ to AGND: -0.3 V to +3.9 V; (9)CLK. to AGND: -0.3 V to +3.9 V; (10)VIN+ to AGND: -0.3 V to AVDD + 1.3 V; (11)VIN. to AGND: -0.3 V to AVDD + 1.3 V; (12)VREF to AGND: -0.3 V to AVDD + 0.2 V; (13)SENSE to AGND: -0.3 V to AVDD + 0.2 V; (14)REFT to AGND: -0.3 V to AVDD + 0.2 V; (15)REFB to AGND: -0.3 V to AVDD + 0.2 V; (16)SDIO/DCS to DRGND: -0.3 V to DRVDD + 0.3 V; (17)PDWN to AGND: -0.3 V to +3.9 V; (18)CSB to AGND: -0.3 V to +3.9 V; (19)SCLK/DFS to AGND: -0.3 V to +3.9 V; (20)OEB to AGND: -0.3 V to +3.9 V; (21)Storage Temperature Range: –65℃ to +125℃; (22)Operating Temperature Range: –40℃ to +85℃; (23)Lead Temperature (Soldering 10 Sec): 300℃; (24)Junction Temperature: 150℃.

Features

AD9233BCPZ-125 features: (1)1.8 V analog supply operation; (2)1.8 V to 3.3 V output supply; (3)SNR = 69.5dBc (70.5dBFS) to 70 MHz input; (4)SFDR = 85dBc to 70 MHz input; (5)Low power: 395mW @ 125 MSPS; (6)Differential input with 650 MHz bandwidth; (7)On-chip voltage reference and sample-and-hold amplifier; (8)DNL = ±0.15 LSB; (9)Flexible analog input: 1 V p-p to 2 V p-p range; (10)Offset binary, Gray code, or twos complement data format; (11)Clock duty cycle stabilizer; (12)Data output clock; (13)Serial port control; (14)Built-in selectable digital test pattern generation; (15)Programmable clock and data alignment.

Diagrams